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Пожалуйста, помогите разобраться с задачей. Инвертор, в нём MOSFETы, как ключи. Ответы не нужны, просто показать направление решения, поскольку желаю разобраться сам.
Прошу пардону, задание на буржуйском языке.
For many purposes of gate design, we can model a MOSFET used as a switch simply as as an ideal switch and an "on-state resistor" RON. This is the SR model.
Assuming this model for the MOSFET, consider the inverter in the figure. This inverter is intended to be used as an element in a logic family with NAND and NOR gates.
The static discipline required for this family is:
VS=5.0V, VOH=4.5V, VIH=4.0V, VIL=1.5V, VOL=1.0V.
What is the low noise margin (in Volts)?
0,5
What is the high noise margin (in Volts)?
0,5
What is the width of the forbidden region (in Volts)?
2,5
Suppose that the threshold voltage for the MOSFET is VT=2.0V and RON=9000.0.
What is the minimum value of the pullup resistor RPuI (in Ohms) for which this inverter can obey the required static discipline?
Now, consider the NAND gate of this family. What is the minimum value of the pullup resistor RPuA (in Ohms) for which this inverter can obey the required static discipline?
How about the NOR gate of this family. What is the minimum value of the pullup resistor RPuO (in Ohms) for which this inverter can obey the required static discipline?
Assume that we implemented this family with the minimum pullup resistors that you have already calculated.
What is the maximum power (in Watts) consumed by the inverter?
What is the maximum power (in Watts) consumed by the NAND?
What is the maximum power (in Watts) consumed by the NOR?
Часть ответов я сам нашел (выделено курсивом), теперь проблема с расчетами.
Заранее спасибо за помощь.
С уважением,
Анатолий
Раздел: Песочница или Вопрос-Ответ
Пожалуйста, помогите разобраться с задачей. Инвертор, в нём MOSFETы, как ключи. Ответы не нужны, просто показать направление решения, поскольку желаю разобраться сам.
Прошу пардону, задание на буржуйском языке.
For many purposes of gate design, we can model a MOSFET used as a switch simply as as an ideal switch and an "on-state resistor" RON. This is the SR model.
Assuming this model for the MOSFET, consider the inverter in the figure. This inverter is intended to be used as an element in a logic family with NAND and NOR gates.
The static discipline required for this family is:
VS=5.0V, VOH=4.5V, VIH=4.0V, VIL=1.5V, VOL=1.0V.
What is the low noise margin (in Volts)?
0,5
What is the high noise margin (in Volts)?
0,5
What is the width of the forbidden region (in Volts)?
2,5
Suppose that the threshold voltage for the MOSFET is VT=2.0V and RON=9000.0.
What is the minimum value of the pullup resistor RPuI (in Ohms) for which this inverter can obey the required static discipline?
Now, consider the NAND gate of this family. What is the minimum value of the pullup resistor RPuA (in Ohms) for which this inverter can obey the required static discipline?
How about the NOR gate of this family. What is the minimum value of the pullup resistor RPuO (in Ohms) for which this inverter can obey the required static discipline?
Assume that we implemented this family with the minimum pullup resistors that you have already calculated.
What is the maximum power (in Watts) consumed by the inverter?
What is the maximum power (in Watts) consumed by the NAND?
What is the maximum power (in Watts) consumed by the NOR?
Часть ответов я сам нашел (выделено курсивом), теперь проблема с расчетами.
Заранее спасибо за помощь.
С уважением,
Анатолий
Раздел: Песочница или Вопрос-Ответ